Electronic circuits, such as integrated microcircuits, are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microcircuit devices typically involves many steps, sometimes referred to as the “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microcircuit fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators. These steps aid in the discovery of errors in the design, and allow the designers and engineers to correct or otherwise improve the design. These various microcircuits are often referred to as integrated circuits (IC's).
Several steps are common to most design flows. Initially, the specification for a new circuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit is described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors, and capacitors) that will be used in the circuit, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. The relationships between the electronic devices are then analyzed, to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as “system level verification.” Additionally, preliminary timing estimates for portions of the circuit are often made at this stage, using an assumed characteristic speed for each device, and incorporated into the verification process.
Once the components and their interconnections are established, the design is again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design. The geometric elements, which typically are polygons, define the shapes that will be created in various layers of material to manufacture the circuit. Typically, a designer will select groups of geometric elements representing circuit device components (e.g., contacts, channels, gates, etc.) and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Lines are then routed between the geometric elements, which will form the wiring used to interconnect the electronic devices. Layout tools (often referred to as “place and route” tools), such as Mentor Graphics' IC Station or Cadence's Virtuoso, are commonly used for both of these tasks.
As indicated, device verification often takes place prior to the actual manufacturing of the device. Accordingly, as stated, hardware description languages are employed to model the hardware and act as an embodiment for testing purposes. However, testing and verification of physical devices also occurs after manufacturing. As a result, distinguishing between verification at the design level and at the physical level is not always made in the balance of this disclosure. Furthermore, device is used interchangeably to refer to a physical embodiment of the device and the models or design of the device.
During the verification stages of device development designers subject the device to numerous tests. Some tests are generated randomly with the assistance of various test engines. While other tests are created by designers to specifically test or “exercise” select portion of the device. Ideally, enough tests are used such that all portions of a device are tested. A portion or portions of a device design exercised by a select test are often said to be “covered” by that test. Electronic design automation tools may assist in generating and carrying out tests upon a device. For example, ModelSim or Questa, both available from Mentor Graphic Corporation of Wilsonville, Oreg., may be employed to assist in performing this type of verification. Additionally, electronic design automation tools may be employed to assist in monitoring which areas of the device are covered by selected tests.
Due to the complex and interconnected nature of modern electronic device, such as integrated circuits, a small revision in one area of the design may affect the functionality of another area of the design. As a result, even small revisions of a design often require retesting of the entire design. This process can be extremely complicated. For example, a modern integrated circuit may have over 100 million gates. Running tests that would exercise each of these 100 million gates is often accomplished by executing the tests upon many computers networked in parallel. However, even with thousands of computers processing concurrently, it will take days to complete enough tests that exercise each of the 100 million gates.
This process of retesting a device after some change has been made is often referred to as regression testing. Ideally a regression test includes just enough tests that exercise each portion of the design. Often times this requires that modern designs be subject to a set of 10,000 or more tests. This set of tests typically is executed each time a small design change is made. After each set of tests is executed, any test failures must be analyzed and the design revised and retested accordingly.
As indicated above, this process can be quite time consuming and burdensome. Adding to the complexity is determining which areas of the design contributed to specific test failures. During the early stages of device design hundreds of the tests may result in a failure. Accordingly, it is not trivial to determine which areas of the device design need to be revised. Historically, designers would assume that all areas of the design not covered by a test and all areas of a design covered by failed tests needed revising. However, many tests cover multiple areas of a device. As a result assuming all areas covered by failed tests increases the design time and ultimately the time until the product may reach the market.